The present invention relates to an input protection circuit of a semiconductor apparatus, and more particularly to an electrostatic destruction prevention protection circuit.
Currently, among semiconductor integrated circuits, CMOS-ICs (Complementary Metal Oxide Semiconductor-Integrated Circuits) are becoming a main stream since they consume low power and achieve a high degree of integration. A MOS transistor used for such a CMOS-IC is formed by the following process. First, a thin oxide film, so called a gate oxide film, is formed on a semiconductor substrate. Second, electrodes are formed on this gate oxide film. Third, a source and a drain are formed separately on the semiconductor substrate. When an electrostatic surge enters from outside (input terminal) into a MOS transistor formed by the above-described process, the gate oxide film is easily destroyed. Therefore, electrostatic destruction prevention protection circuits are formed near the input terminal and the output terminal of the semiconductor apparatus, respectively.
A protective resistor formed between the internal circuit and the input terminal, an electrostatic destruction prevention protection circuit having a protective transistor formed between the internal circuit and the power source potential line that supplies power source electric potential, and an electrostatic destruction prevention protection circuit having a protective transistor formed between the internal circuit and a ground potential line that supplies the ground electric potential are exemplary electrostatic destruction prevention protection circuits. The protection circuit delays the surge current while the surge current is transmitted to the power source potential line or ground potential line for the internal circuit so that an excessive voltage will not be applied to, for example, the gate electrode of an input transistor that constitutes an inverter closest to the input terminal of the internal circuit. Moreover, the protective transistor bypasses the surge current from the input terminal to the power source or the ground.
In recent years as semiconductors are scaled down, the gate oxide film of an input transistor is getting thinner. As a result, the gate oxide film is also becoming less breaking resistant. Hence, the resistance of the above-described protective resistor needs to be increased. Moreover, as the chip size is increased, the wire length of the power source potential line from the power source terminal to the protective transistor and the wire length of the ground potential line from the ground terminal to the protective transistor are also increased. As a result, the parasitic resistance of each of these lines is increased. This parasitic resistance delays the surge current, which has passed through the protective transistor, from flowing into the internal circuit power source line and the ground line. As a result, the gate oxide film of the inverter becomes less breaking resistant.